Flip-flops and latches are common elements of circuits. A flip-flop receives a data signal on an input data terminal. The input data terminal is typically denoted by the symbol D. Upon receiving a clock signal on a clock terminal, the flip-flop stores (latches) the data signal and provides the data signal on an output data terminal. The clock terminal is typically denoted by the symbol CK, and the output data terminal is typically denoted by the symbol Q. The data signal is latched upon the occurrence of an edge of the clock signal. Herein, the terms “terminal” and “pin” may be considered interchangeable.
A latch operates in a manner similar to a flip-flop, except that the latch is “open” during substantially the entire interval while the clock signal is asserted. In other words, for a latch, the signal propagates from D through the latch to Q during substantially the entire time while the clock signal is asserted. When the clock signal is no longer asserted, the latch “closes”, e.g. the signal from D is no longer propagated to Q. The Q terminal retains the value of the signal at D when the latch closed.
After the clock signal arrives at CK, the data signal must remain stable for the hold time in order for the data signal to be properly latched. This is true for both flip-flops and latches. Another consideration is the period of time during which the data signal must be stable before the clock signal arrives at CK. This is referred to as the setup time. The data signal must arrive at D and be stable there for a period of time equal to or exceeding the setup time in order for the data signal to be properly latched. Both flip-flops and latches are characterized by setup times.
For a flip-flop, the triggering edge of the clock signal is the clock signal edge that causes the flip-flop to latch the data signal. The triggering edge may be either the rising or falling edge of the clock signal. For a latch, the edge of the clock signal that causes the latch to open is referred to as the opening edge of the latch. The edge of the clock signal that causes the latch to close is referred to as the closing edge of the latch. The rising edge of the clock signal may serve as either the opening or closing edge of a latch. Likewise, the falling edge of the clock signal may serve as either the opening or closing edge of a latch.
Flip-flops and latches are clocked devices typically employed as sequential circuit elements. The timing of their operation is controlled by the timing of the clock signal. Non-clocked devices are also typically found in circuits. Such devices operate independently of a clock signal, and may be referred to collectively as “combinational” circuit elements. Examples of combinational elements include logic gates (AND, OR, inverter, NOR, NAND, etc. gates). Both clocked and combinational circuit elements have an associated propagation delay. The propagation delay of flip-flops and latches is the time that it takes the data signal to propagate from D to Q, once the clock signal is received at CK. The propagation delay of combinational elements, and collections thereof, is the time it takes for changes in the data signal(s) to the combinational elements to be reflected at the output(s) of the combinational elements.
A circuit element may be characterized by different propagation delays for high-low (falling) and low-high (rising) signal transitions. For example, an AND gate in a circuit may be characterized by a first input-to-output propagation delay for rising input signals, and second input-to-output propagation delay for falling input signals.
The propagation delay of a flip-flop is typically specified in terms of the time it takes a data signal at the D terminal to reach the Q terminal after the clock signal arrives at the CK terminal. This propagation delay may be referred to as the CK-Q delay of the flip-flop.
One propagation delay of a latch is typically specified in terms of the time it takes a data signal at the D terminal to reach the Q terminal after the opening clock edge arrives at the CK terminal. This propagation delay may be referred to as the CK-Q delay of the latch. The CK-Q delay of the latch may be employed in situations where the data signal arrives at the D terminal of a closed latch. Another propagation delay of a latch is typically specified in terms of the time it takes a data signal at the D terminal to reach the Q terminal when the data signal arrives at the D terminal of an open latch. This propagation delay may be referred to as the D-Q delay of the latch.
An important consideration for circuit designers is the tolerance for signal delays inherent in a circuit design. For example, in a circuit including a latch, it may be important for the circuit designer to know that the data signal arrives at D of the latch within the setup time of the latch, with five nanoseconds to spare. This spare time may be referred to as the “slack time” of the latch in the circuit in question. Among other things, the slack time for an element tells the designer whether the circuit design can tolerate additional delays in the data signal prior to the element. Where the slack time for an element is substantial, it may be possible for the circuit designer to insert additional or slower combinational logic before (“upstream” from) the element, or to rearrange the circuit design so that the slack time of the element is reduced by shifting the benefit of the slack time to parts of the design that come after (“downstream” from) the element. Herein, the term “upstream”, in relation to a circuit element, refers to points in a circuit that a signal of interest reaches before it reaches the element. “Downstream” refers to points in the circuit that the signal reaches after it reaches the element.
A slack time may be positive, indicating that there is some spare time built into the timing. A slack time may also be negative, indicating that signals do not propagate in sufficient time to meet the timing requirements of the circuit.
Existing approaches to determining the slack time for latches have involved attempts to balance the slack time of the latch with the slack time of the next clocked element downstream from the latch. These approaches have proven problematic and have led to complex implementation code, misleading or unexpected slack times at points in the circuit, and confusing slack time reports.